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NXP Semiconductors /LPC408x_7x /GPDMA /INTTCCLEAR

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Interpret as INTTCCLEAR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (INTTCCLEAR0)INTTCCLEAR0 0 (INTTCCLEAR1)INTTCCLEAR1 0 (INTTCCLEAR2)INTTCCLEAR2 0 (INTTCCLEAR3)INTTCCLEAR3 0 (INTTCCLEAR4)INTTCCLEAR4 0 (INTTCCLEAR5)INTTCCLEAR5 0 (INTTCCLEAR6)INTTCCLEAR6 0 (INTTCCLEAR7)INTTCCLEAR7 0RESERVED

Description

DMA Interrupt Terminal Count Request Clear Register

Fields

INTTCCLEAR0

Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.
INTTCCLEAR1

Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.
INTTCCLEAR2

Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.
INTTCCLEAR3

Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.
INTTCCLEAR4

Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.
INTTCCLEAR5

Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.
INTTCCLEAR6

Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.
INTTCCLEAR7

Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.
RESERVED

Reserved. Read value is undefined, only zero should be written.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data